The Memory Wall
Memory sub-systems have long been a critical bottleneck limiting the performance of computation and telecommunications systems. Fueled by technology scaling, integrated circuit logic performance and off-chip memory bit-cost have improved by a phenomenal four orders of magnitude in the past three decades, yet, over the same time period, off-chip memory performance has remained flat. With the internet revolution and the explosion of mobile systems in the past decade, the performance requirements for memory sub-systems have greatly accelerated, making memory the most critical performance limiter in nearly all modern systems.
Due to this "memory wall," there has been a growing need to embed as much memory as possible on-chip to maintain the performance of the memory sub-system and reduce power consumption. Mainstream integrated circuits in a wide range of applications (MPU's, DSP's, GPU's, etc.) are dedicating 50% or more of the die area to embedded memory. For networking and L2/L3 cache applications in particular, there is a huge demand for an embedded memory solution that combines the highest possible random cycle performance with the highest possible density.
The Memory Scalability Crisis
Despite its large cell area which limits the amount of on-chip memory, 6T-SRAM has been the embedded memory technology of choice. Its dominance is due to its high performance as well as its inherent CMOS compatibility. Further, the presence of positive regenerative feedback in 6T-SRAM cell provides large cell read/write margins and a manufacturing robustness that historically has provided the lowest time and cost of development among embedded memory technologies.
As CMOS transistor geometry and voltage scaling become limited by fundamental effects such as increased random Vth-variability, gate dielectric leakage, and sub-threshold slope, 6T-SRAM stability and manufacturing margins have dramatically worsened. Further, the layout complexity of 6T-SRAM is pushing lithography tools and processes to their limit. As a result, at 45nm technology node and beyond, 6T-SRAM scalability has been diminished and its time and cost of development has significantly lengthened.
Failed Embedded Memory Alternatives
Alternative embedded memory technologies to 6T-SRAM, such as eDRAM, Magneto-resistive RAM, Ferro-electric RAM, Phase-change RAM, and Floating-body DRAM, have been the subject of research and development for many years. Few of these alternative technologies, however, have proven to be viable and none have gained traction as an embedded memory solution. Inability to match 6T-SRAM in performance, poor scalability/manufacturability, and high cost due to incompatibility with CMOS logic processes, have been among the top limiters of these alternative embedded memory technologies.
The most researched alternative to 6T-SRAM, embedded DRAM (eDRAM), has a 3-4x higher macro density advantage over 6T-SRAM, but has been limited by long development time, high cost, incompatibility with high-speed CMOS logic process and poor scalability. Also, eDRAM’s destructive read characteristic has limited its random cycle performance, negating the potential memory hierarchy performance benefit from its higher embedded cache density. Other alternative candidates also suffer from limited random-cycle performance and poor scalability.
