Best Combined Speed and Density
The Thyristor-RAM macro provides the highest combination of performance and density among all embedded memories solutions. A Thyristor-RAM macro matches 6T-SRAM in performance while providing 2-3x higher macro density, and lower power consumption.

Highly Scalable
Given the difference in physics of operation between the Thyristor-RAM and a FET, Thyristor RAM scaling is not affected by fundamental variability issues (caused by random dopant fluctuation and line edge roughness) that limit 6T-SRAM (and other “FET-based” RAMs) scaling. In fact, Thyristor-RAM write margin improves with geometry scaling while large read current margin of several decades is maintained. The simple straight-line layout of Thyristor-RAM cell further enhances its scalability given the limitations of lithography tools at deep nano-scale geometries. Further, CMOS technology trends such as the emergence of Bulk/SOI FinFET and MUGFET technologies as candidates for 22nm and beyond further improve Thyristor-RAM characteristics.

Highly Scalable Density and Performance

Simple Layout Helps Lithography Scaling

Actual Thyristor-RAM Bit-Cell Array

Good Synergy with Alternatives to Planar CMOS

Easy Integration on Bulk and SOI
The Thyristor-RAM is fully CMOS compatible and can be readily integrated with a baseline CMOS technology on either Bulk or SOI substrates without any impact on the baseline technology/transistors.

Bulk Thyristor-RAM Cell

SOI Thyristor-RAM Cell

For questions and more information, please contact us at info@t-ram.com