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Pipelined Burst SRAM
Pipelined Read, Double Cycle Deselect
Patented T-RAM memory cell technology with superior
speed/density product over
6-transistor SRAMs
18Mb in 256k x72, 512k x36, 512k x32, and 1M x18 bit
organization
36Mb in 512K x72, 1M x36, 1M x32,
and 2M x18 bit organization
72Mb in 1M x72,
2M x36, 2M x32, and 4M x18 bit organization
Common I/O
Single 2.5V or
3.3V power supply (VDD)
Dedicated 1.8V,
2.5V or 3.3V nominal I/O buffer supply (VDDQ)
Input clock to
latch on rising edge address, data, and control signals
Pipelined Read
Operation
ADSP#, ADSC#, ADV# Burst Control
Pins
Linear or interleaved
burst modes
Individual Byte
Write and Global Write capability
Byte write capability
2 cycle Enable,
2 cycle Disable
Three chip enable for simple depth
expansion
Sleep mode capability
(ZZ)
IEEE1149.1 Compatible
JTAG serial boundary scan test access port (TAP)
JEDEC Standard
209-pin (11 x 19) Ball Grid Array (BGA) package, 14mm
x 22mm,
1.00mm pitch
100-pin TQFP,
JEDEC Standard 119-pin (7 x 17) Ball Grid Array (BGA)
package and
165-pin (11 x 15) FBGA
Density |
Org. |
Cycle
Time |
VDD
/ VDDQ |
Packages |
T-RAM
Part No. |
Data
Sheet Rev. |
18Mb |
x36
x32
x18 |
4.0/4.4/5.0
|
2.5 / 2.5
2.5 / 1.8 |
100 TQFP
119 BGA
165 FBGA |
|
0.0 |
18Mb |
x36
x32
x18 |
4.0/4.4/5.0
|
3.3 / 3.3
3.3 / 2.5 |
100 TQFP
119 BGA
165 FBGA |
|
0.0 |
18Mb |
x72 |
4.0/4.4/5.0
|
2.5 / 2.5
2.5 / 1.8 |
209 BGA |
|
0.0 |
36Mb |
x36
x32
x18 |
4.0/4.4/5.0
|
2.5 / 2.5
2.5 / 1.8 |
100 TQFP
119 BGA
165 FBGA |
|
0.0 |
36Mb |
x36
x32
x18 |
4.0/4.4/5.0
|
3.3 / 3.3
3.3 / 2.5 |
100 TQFP
119 BGA
165 FBGA |
|
0.0 |
36Mb |
x72 |
4.0/4.4/5.0
|
2.5 / 2.5
2.5 / 1.8 |
209 BGA |
|
0.0 |
72Mb |
x36
x32
x18 |
4.0/4.4/5.0
|
2.5 / 2.5
2.5 / 1.8 |
100 TQFP
119 BGA
165 FBGA |
|
0.0 |
72Mb |
x36
x32
x18 |
4.0/4.4/5.0
|
3.3 / 3.3
3.3 / 2.5 |
100 TQFP
119 BGA
165 FBGA |
|
0.0 |
72Mb |
x72
|
4.0/4.4/5.0
|
2.5 / 2.5
2.5 / 1.8 |
209 BGA |
|
0.0 |
|
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