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eZt™ (Enhanced Zero-Turnaround) Late-Late-Write
SRAM
Pipelined Read
Patented T-RAM memory cell technology with superior
speed/density product over
6-transistor SRAMs
18Mb in 256k x72, 512k x36, and 1M x181 bit organization
36Mb in 512K x72, 1M x36, and 2M x181 bit organization
72Mb in 1M x72, 2M x36, and 4M x181 bit organization
Common I/O
Single 1.8V power supply (VDD)
Dedicated 1.8V nominal I/O buffer supply (VDDQ)
Input clock to latch on rising edge address, data, and
control signals
Pipelined Read Operation
Linear or interleaved burst modes
Single R/W# (Read/Write) control pin
Full data coherency
Byte write capability
E2, E3, EP2, and EP3 chip enables for simple depth expansion
Programmable output driver impedance (ZQ)
Dual Cycle Deselect (DCD)
IEEE1149.1 Compatible JTAG serial boundary scan test
access port (TAP)
JEDEC Standard 209-pin (11 x 19) Ball Grid Array (BGA)
package, 14mm x 22mm, 1.00mm pitch
JEDEC Standard 119-pin (7 x 17) Ball Grid Array (BGA)
package2 and 165-pin (11 x 15) FBGA2
Density |
Org.1 |
Cycle
Time |
VDD
/ VDDQ |
Packages2 |
T-RAM
Part No. |
Data
Sheet Rev. |
18Mb |
x72
x36 |
4.0/4.4/5.0 |
1.8 / 1.8 |
209 BGA |
|
0.0 |
36Mb |
x72
x36 |
4.4/5.0/5.5 |
1.8 / 1.8 |
209 BGA |
|
0.0 |
72Mb |
x72
x36 |
4.4/5.0/5.5 |
1.8 / 1.8 |
209 BGA |
|
0.0 |
1.
For the x18 organization, please contact T-RAM
Marketing.
2. 119BGA and
165FBGA are offered for only x36 and x18 organizations.
For these
packages,
please contact T-RAM Marketing. |
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